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I
[AK4220]
AK4220
7:3 Audio Switch and 6:3 Video Switch
GENERAL DESCRIPTION The AK4220 is an AV Switch with 7:3 Audio Switches and 6:3 Video Switches. Using CMOS process to offer the high performance with low power consumption. In the Audio section, on-chip differential input circuit could separate the external ground noise. The AK4220 integrates a pop noise free circuit for power on/pff. The AK4220 is offered in a space saving 64-pin LQFP package, ideal for car navigation applications. FEATURES 1. Audio Section * Selector for 7 inputs and 3 outputs * Differential Input Circuit for Ground Noise Cannel * THD+N: -92dB (@1Vrms) * Dynamic Range: 96dB * Channel-Independent Output Off * Pop Noise Free Circuit for Power On/Off * Channel-Independent Input Detection Circuit 2. Video Section * Selector for 6 inputs and 3 outputs * Six Composite Signal Inputs * Video Driver for Composite Signal Output (+6dB) * Channel-Independent Hi-Z Output * On-Chip Sync-tip Clamp Circuit * Frequency Range: 6MHz * S/N: 74dB * Input Detection Circuit 3. Control Section * Serial P I/F (I2C, 4-wires serial) * Five Programmable Output pins 4. Power Supply * Analog: 4.5V ~ 5.5V * Digital: 3.0V ~ 3.6V * Low Power Consumption: 186mW 5. Ta = -40 85 C 6. Package: 64pin LQFP
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[AK4220]
AV D D 40k (typ) AV S S
LIN + 1
40k (typ) LO U T 1 VCO M 40k (typ)
GND1 40k (typ) 40k (typ) R IN + 1 40k (typ)
MU T E T
ROUT1
In put #1
MU T E T
O utput #1
LIN + 2 GND2 R IN + 2
(s am e circ uit) In put #2 (s am e circ uit) LO U T 2
LIN + 3 GND3 R IN + 3
(s am e circ uit) In put #3 O utput #2
ROUT2
LIN + 4 GND4 R IN + 4
(s am e circ uit) In put #4 (s am e circ uit) LO U T 3
LIN + 5 GND5 R IN + 5
(s am e circ uit) In put #5 O utput #3
ROUT3
LIN + 6 GND6 R IN + 6
(s am e circ uit) In put #6
LIN + 7 GND7 R IN + 7
(s am e circ uit) In put #7 AD ET L
R VCO M MU T E T
O s cillator B ias ADET R
Figure 1. Audio Block
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[AK4220]
VVDD1 VVDD2 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VFB1 +6dB Video Drivers VVSS1 VVSS2 VVSS3 VOUT1
+6dB
VOUT2
VFB2
+6dB
VOUT3
VFB3
Sync DET
Sync-tip TEST PDN IICN SDA/CDTI SCL/CCLK INT PDN CAD1/CSN CAD0/CDTO Control Registers Clamp (A/V control) DVDD DVSS (open drain) Q0 Q1 Q2 Q3 Q4
Figure 2. Video & Control Block
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[AK4220]
Ordering Guide
AK4220VQ AKD4220 -40 +85C 64pin LQFP (0.5mm pitch) Evaluation board for AK4220
Pin Layout
GND2 48 RIN+1 47 LIN+1 46 GND1 45 ROUT3 44 LOUT3 43 ROUT2 42 LOUT2 41 ROUT1 40 LOUT1 39 AVSS 38 VCOM 37 MUTET 36 R 35 AVDD 34 VIN6 33 VIN5 32 IICN 31 VIN4 30 VVSS1 29 VIN3 28 VVDD1 27 VIN2 26 VVSS3 25 VIN1 24 VVSS2 23 VFB3 22 VOUT3 21 VVDD2 20 VFB2 19 VOUT2 18 15 VOUT1 13 DVDD TEST 17 16 VFB1 14 DVSS CAD1 CAD0 PDN SDA
49 LIN+2 50 RIN+2 51 GND3 52 LIN+3 53 RIN+3 54 GND4 55 LIN+4 56 RIN+4 57 GND5 58 LIN+5 59 RIN+5 60 GND6 61 LIN+6 62 RIN+6 63 GND7 RIN+7 64 LIN+7
AK4220
Top View
SCL
INT
Q0
Q1
10 Q2
11 Q3
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1
2
3
4
5
6
7
8
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[AK4220]
PIN/FUNCTION
No. 1 2 Pin Name RIN+7 PDN CAD1 CSN SCL CCLK SDA CDTI CAD0 CDTO INT Q0 Q1 Q2 Q3 Q4 DVDD DVSS VOUT1 VFB1 TEST VOUT2 VFB2 VVDD2 VOUT3 VFB3 VVSS2 VIN1 VVSS3 VIN2 VVDD1 VIN3 VVSS1 VIN4 IICN VIN5 VIN6 AVDD I/O I I I I I I I/O I I O O O O O O O O I I O I O I I I I I I I I Function Rch Audio Positive Input 7 Power down Mode "L": Power down, Reset "H": Power up The AK4220 should always be reset upon power-up. Chip Address1 (IICN pin = "L") Chip Selector (IICN pin = "H") Control Clock Input (IICN pin = "L") Control Clock Input (IICN pin = "H") Control Data Input/Output (IICN pin = "L") Control Data Input (IICN pin = "H") Chip Address0 (IICN pin = "L") Control Data Output (IICN pin = "H") Interrupt Parallel Output 0 (open drain output) Parallel Output 1 (open drain output) Parallel Output 2 (open drain output) Parallel Output 3 (open drain output) Parallel Output 4 (open drain output) Digital Power Supply Normally connected to DVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Digital Ground Video Output 1 Video Feedback 1 Test pin, Connected to VVSS. Video Output 2 Video Feedback 2 Video Power Supply, 5V Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Video Output 3 Video Feedback 3 Video Ground2, 0V Video Input 1 Video Ground3, 0V Video Input 2 Video Power Supply, 5V Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Video Input 3 Video Ground1, 0V Video Input 4 Control Mode Selection "L"(Connected to VVSS): IIC Bus "H" (Connected to VVDD): 4-wire Serial Video Input 5 Video Input 6 Audio Power Supply, 5V Normally connected to AVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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PIN/FUNCTION (Continued)
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 R MUTET VCOM AVSS LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 GND1 LIN+1 RIN+1 GND2 LIN+2 RIN+2 GND3 LIN+3 RIN+3 GND4 LIN+4 RIN+4 GND5 LIN+5 RIN+5 GND6 LIN+6 RIN+6 GND7 LIN+7 O O O O O O O O O I I I I I I I I I I I I I I I I I I I I Current Setting for Oscillator Normally connected to AVSS with a 12k1%resistance. Audio Common Voltage Output2 Normally connected to AVSS with a 1F ceramic capacitor. Audio Common Voltage Output1 (Figure 3) Normally connected to AVSS with a 0.1F ceramic capacitor in parallel with a 2.2F electrolytic capacitor. Audio Ground, 0V Lch Audio Output 1 Rch Audio Output 1 Lch Audio Output 2 Rch Audio Output 2 Lch Audio Output 3 Rch Audio Output 3 Audio Input Ground1 Lch Audio Positive Input 1 Rch Audio Positive Input 1 Audio Input Ground 2 Lch Audio Positive Input 2 Rch Audio Positive Input 2 Audio Input Ground 3 Lch Audio Positive Input 3 Rch Audio Positive Input 3 Audio Input Ground 4 Lch Audio Positive Input 4 Rch Audio Positive Input 4 Audio Input Ground 5 Lch Audio Positive Input 5 Rch Audio Positive Input 5 Audio Input Ground 6 Lch Audio Positive Input 6 Rch Audio Positive Input 6 Audio Input Ground 7 Lch Audio Positive Input 7
Note: All digital input pins (PDN, CAD1-0, SCL and SDA pins) must not be left floating.
AVDD
35k(typ) VCOM 35k(typ) 2.2uF 0.1uF
AVSS
Figure 3. VCOM Circuit
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[AK4220]
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Pin Name LIN+1-LIN+7, RIN+1-RIN+7, LOUT1-LOUT3, ROUT1-ROUT3,VIN1-VIN6, VOU1-VOUT3, VFB1-VFB3, Q0-Q4, INT TEST Setting These pins should be open.
Analog
Digital
These pins should be connected to DVSS.
ABSOLUTE MAXIMUM RATINGS (AVSS = VVSS1-3 = DVSS = 0V; Note: 1) Parameter Symbol min -0.3 AVDD Power Supplies Audio -0.3 VVDD1 Video -0.3 VVDD2 Video -0.3 DVDD Digital |AVSS-DVSS| (Note: 2) GND1 |AVSS-VVSS1| (Note: 2) GND2 |AVSS-VVSS2| (Note: 2) GND3 |AVSS-VVSS3| (Note: 2) GND4 Input Current (any pins except for supplies) IIN Audio Input Voltage VINA -0.3 (LIN+1-7, RIN+1-7, GND1-7 pins) Video Input Voltage1 VINV1 -0.3 (VIN1-6, IICN pins) Video Input Voltage2 VINV2 -0.3 (VFB1-3, TEST pins) Digital Input Voltage VIND -0.3 (PDN, CAD1-0, SCL ,SDA pins) Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65 Note: 1. All voltages with respect to ground. Note: 2. AVSS, VVSS1-3 and DVSS must be connected to the same analog ground plane.
max 6.0 6.0 6.0 6.0 0.3 0.3 0.3 0.3 10 AVDD+0.3 VVDD1+0.3 VVDD2+0.3 DVDD+0.3 85 150
Units V V V V V V V V mA V V V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS = VVSS1-3 = DVSS = 0V; Note: 1) Parameter Symbol min typ Audio Power Supplies AVDD 4.5 5.0 Video (Note: 4) (Note: 3) VVDD1 4.5 5.0 Video (Note: 4) VVDD2 4.5 5.0 Digital DVDD 3.0 3.3 VVDD1 - AVDD -0.3 0 VDD1 VVDD2 - AVDD -0.3 0 VDD2 Note: 3. The power-up sequence between AVDD, VVDD1, VVDD2 and DVDD is not critical. Note: 4. VVDD1 and VVDD2 must be the same voltage.
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
max 5.5 5.5 5.5 3.6 +0.3 +0.3
Units V V V V V V
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[AK4220]
ANALOG CHARACTERISTICS (AUDIO) (Ta=25C; AVDD = VVDD1-2 = 5V, DVDD =3.3V; AVSS = VVSS1-3 = DVSS = 0V; Signal Frequency=1kHz, Measurement Frequency=20Hz20kHz, unless otherwise specified) Parameter min typ max Units S/(N+D) Input=0dBV 82 92 dB DR (0dBV) Input=-60dBV, A-weighted 88 96 dB S/N (0dBV) Input=0ff, A-weighted 88 96 dB Input Impedance (Note: 5) 20 k Maximum Input Voltage (Note: 6) 1 Vrms Gain -0.5 0 0.5 dB Interchannel Isolation (Note: 7) 100 dB Interchannel Gain Mismatch 0.2 dB Gain Drift 20 ppm/C Load Resistance (Note: 8) R1+R2 (Figure 4) 5 k 400 pF Load Capacitance C1 (Figure 4) 30 pF C2 (Figure 4) Power Supply Rejection (Note: 9) 50 dB Input Detection Circuit Input Reception 1kHz (Note: 10) -43 -31 -26 dBV Input Reception Adjustment Gain Step (Note: 11) 3 dB Note: 5. Connected GND1-7 to GND using a capacitor for AC-coupling. Note: 6. The Input Voltage meets S/(N+D)>82dB Note: 7. Between all channels of LIN1-7 and RIN1-7. Note: 8. The output resistance of audio output (LOUT1-3 and ROUT1-3) are less than l0(typ). Note: 9. Applied to AVDD, VVDD1-2 and DVDD with a sine wave (1kHz, 50mVpp). Note: 10. Detect an instant value. 31dBV=+40mV0p. If the input voltage is smaller than the detection reception value, the signal isn't detected, and if the input voltage is larger than the detection reception value, the signal is detected. The input reception value is proportional to AVDD voltage as of 0.008 x AVDD V0p(typ). Note: 11. Input Reception Adjustment Gain is +6dB-6dB.
R1 300
C3 10uF LOUT1-3 ROUT1-3
R2 4.7k
C21
C22
C1
C2=C21+C22= 30pF(max)
C1= 400pF(max)
Figure 4. Load Resistance R1, R2 and Load Capacitance C1, C2.
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ANALOG CHARACTERISTICS (VIDEO) (Ta=25C; AVDD = VVDD1-2 = 5V, DVDD =3.3V; AVSS = VVSS1-3 = DVSS = 0V; unless otherwise specified) Parameter Conditions min typ max Units At output pin. 0.6 V Sync Tip Clamp Voltage (Note: 12) Gain (Note: 13) Input=0.3Vp-p, 100kHz 5.5 6 6.5 dB Frequency Response (Note: 13) Input=0.3Vp-p, 100kHz to 6MHz. -1.0 1.0 dB Maximum Input Signal f=100kHz, maximum with distortion < 1.0%, 1.5 Vpp gain=6dB(typ). Load Resistance R1+R2(Note: 14) 150 400 pF Load Capacitance C1 (Note: 14) 15 pF C2 (Note: 14) Interchannel Isolation (Note: 15) f=4.43MHz, 1Vpp input. 50 dB S/N Reference Level = 0.7Vpp, CCIR 567 74 dB weighting. BW= 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. % 0.4 chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. Degree 0.9 chrominance &burst are 280mVpp, 4.43MHz. Input Detection Circuit Input Reception (Note: 16) 0.04 0.07 0.1 Vpp Note: 12. SAGN bit="1", DC output. There is no specification for using the Sag Compensation circuit (SAGN bit="0"). Sync Tip Clamp Voltage is proportional to AVDD voltage, VOUT=0.17 x AVDD V(typ). Note: 13. If SAGN bit="0" for using the Sag Compensation circuit, the measurement point is between C3 and R1 of Figure 5. If SAGN bit="1" for DC output, the measurement point is video output pin. Note: 14. See Figure 5 and Figure 6. Note: 15. Between all channels of VIN1-6. Note: 16. If the input voltage is smaller than the detection reception value, the signal isn't detected. If the input voltage is larger than the detection reception value, the signal is detected. The input reception value is proportional to AVDD voltage, 0.014 x AVDD Vpp(typ).
C3 100uF +6dB VOUT VFB C4 2.2uF R1 75
R2 75
C21
C22
C23
C1
C2=C21+C22+C23= 15pF(max)
C1= 400pF(max)
Figure 5. Load Resistance R1, R2 and Load Capacitance C1, C2 (SAGN bit="0", using the Sag Compensation circuit)
R1 75 +6dB VOUT VFB R2 75
C2
C1
C2=15pF(max)
C1=400pF(max)
Figure 6. Load Resistance R1, R2 and Load Capacitance C1, C2 (SAGN bit="1", DC output)
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[AK4220]
DC CHARACTERISTICS (Ta=-4085C; AVDD = VVDD1-2 = 4.55.5V, DVDD =3.03.6V) Parameter Symbol min 70%DVDD VIH High-Level Input Voltage (PDN, SCL,SDA,CAD0-1,TEST,IICN pins) VIL Low-Level Input Voltage (PDN, SCL,SDA,CAD0-1,TEST,IICN pins) DVDD-0.4 VOH High-Level Output Voltage (Iout=-400A) Low-Level Output Voltage VOL (CDTO pin: Iout=400A) VOL (Q0-4, INT pins: Iout=1mA) VOL (SDA pin: Iout=3mA) Input Leakage Current Iin
typ -
max 30%DVDD 0.4 0.4 0.4 10
Units V V V V V V A
Parameter Power Supplies Power Supply Current Normal Operation (PDN pin = "H") AVDD VVDD1+VVDD2 DVDD Power-down mode (PDN pin = "L") AVDD VVDD1+VVDD2 DVDD Total
min
typ
max
Units
(Note: 17) (Note: 18) (Note: 19) 10 10 10 30 A A A A 18 18 1 27 27 2 mA mA mA
50
Note: 17. No input and no load. Note: 18. If the output is DC output (SAGN bit ="1"), the current corresponded to the load resistance is added to no load current (typ. 18mA). Note: 19. All analog input pins are no input, and all digital input pins are fixed to DVSS.
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[AK4220]
SWITCHING CHARACTERISTICS (Ta= -4085C; AVDD = VVDD1-2 = 4.55.5V, DVDD= 3.03.6V, CL= 20pF) Control Interface Timing (I2C Bus, Note: 20) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note: 21) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Capacitive load on bus Cb Control Interface Timing (4-wire serial mode) tCCK 200 CCLK Period tCCKL 80 CCLK Pulse Width Low tCCKH 80 Pulse Width High tCDS 50 CDTI Setup Time tCDH 50 CDTI Hold Time tCSW 150 CSN "H" Time tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" tDCD CDTO Delay tCCZ CSN "" to CDTO Hi-Z Power-down & Reset Timing TPD 150 PDN Pulse Width (Note: 21)
Note: 20. I2C is a registered trademark of Philips Semiconductors. Note: 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 22. The AK4220 should be reset by PDN pin = "L" upon power up.
400 0.3 0.3 50 400
kHz s s s s s s s s s s ns pF ns ns ns ns ns ns ns ns ns ns ns
45 70
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[AK4220]
Timing Diagram
VIH SDA VIL tBUF SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop tLOW tR tHIGH tF tSP VIH
Figure 7. I2C Bus Mode Timing
VIH CSN tCSS tCCK tCCKL tCCKH CCLK tCDH VIH VIL VIH VIL tCDS CDTI C1 C0 VIL
R/W
A4
CDTO
Hi-Z
Figure 8. WRITE/READ Command Input Timing (4-wire serial mode)
tCSW CSN tCSH VIH VIL VIH VIL
CCLK
CDTI
D3
D2
D1
D0
VIH VIL
CDTO
Hi-Z
Figure 9. WRITE Data Input Timing (4-wire serial mode) MS0627-E-00 - 12 2007/05
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[AK4220]
VIH CSN VIL
CCLK
VIH VIL
CDTI
A1
A0
VIH VIL tDCD
CDTO
Hi-Z
D7
D6
D5
50%DVDD
Figure 10. READ Data Output Timing1 (4-wire serial mode)
tCSW CSN tCSH CCLK VIH VIL VIH VIL
CDTI tCCZ CDTO 50%DVDD Hi-Z D2 D1 D0
VIH VIL
Figure 11. READ Data Output Timing2 (4-wire serial mode)
tPD PDN
VIL
Figure 12. Power-down & Reset Timing
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[AK4220]
OPERATION OVERVIEW
Power-down options
The AK4220 should be reset once by bringing PDN pin = "L" upon power-up.
Audio Bias Control Circuit
The AK4220 has an on-chip audio bias voltage control circuit. Bringing BIAS bit to "1", the bias voltage (MUTET pin) smoothly set from AVSS to AVDD/2(typ) by 150ms (typ, Note: 23). The change of BIAS bit from "1" to "0" also makes smooth transient from AVDD/2(typ) to AVSS by 150ms (typ, Note: 23). This feature achieves pop noise free at power-on/off. Note: 23. AVDD=5.0V, the capacitor of MUTET pin is C=1uF. The rise and fall times are proportional to the voltage of AVDD and the capacitor value of MUTET pin.
PDN pin
BIAS bit
"0" (default)
150ms (typ)
"1"
150ms (typ)
"0"
Audio bias level
Figure 13. BIAS bit
Audio Signal Input, Video Signal Input
1. Audio Signal Input The ground noise can be cancelled by the differential input with the same ground for L and R channel. The output of LIN and RIN are the same phase. LIN+1-7, RIN+1-7 and GND1-7 pins must be AC coupled using 0.47uF capacitor. 2. Video Signal Input Tip Sync level is fixed by internal clamp circuit. VIN1-6 pins must be input through 0.47uF capacitor for AC coupling.
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[AK4220]
Input Selector
The AK4220 have 7:3 input selectors for audio input, and 6:3 input selectors for video input. The audio input selectors are set by ASEL12-10bits, ASEL22-20bits and ASEL32-30 bits, and the video input selectors are set by VSEL12-10bits, VSEL22-20bits and VSEL32-30 bits. ASEL12 bit 0 0 0 0 1 1 1 1 ASEL11 bit 0 0 1 1 0 0 1 1 ASEL10 bit 0 1 0 1 0 1 0 1 Input Selector Off (Note: 24) LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 LIN7 / RIN7
(default)
Table 1. Audio Input Selector 1 (LOUT1/ROUT1)
ASEL22 bit 0 0 0 0 1 1 1 1
ASEL21 bit 0 0 1 1 0 0 1 1
ASEL20 bit 0 1 0 1 0 1 0 1
Input Selector Off (Note: 24) LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 LIN7 / RIN7
(default)
Table 2. Audio Input Selector 2 (LOUT2/ROUT2)
ASEL32 bit 0 0 0 0 1 1 1 1
ASEL31 bit 0 0 1 1 0 0 1 1
ASEL30 bit 0 1 0 1 0 1 0 1
Input Selector Off (Note: 24) LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 LIN7 / RIN7
(default)
Table 3. Audio Input Selector 3 (LOUT3/ROUT3)
Note: 24. The audio outputs become common voltage (VCOM) when the input selectors are off. If BIAS bit = "0", the outputs become 0V.
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VSEL12 bit 0 0 0 0 1 1 1 1
VSEL11 bit 0 0 1 1 0 0 1 1
VSEL10 bit 0 1 0 1 0 1 0 1
Input Selector Off (Note: 25) VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A
(default)
Table 4. Video Input Selector 1 (VOUT1) VSEL22 bit 0 0 0 0 1 1 1 1 VSEL21 bit 0 0 1 1 0 0 1 1 VSEL20 bit 0 1 0 1 0 1 0 1 Input Selector Off (Note: 25) VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A
(default)
Table 5. Video Input Selector 2 (VOUT2) VSEL32 bit 0 0 0 0 1 1 1 1 VSEL31 bit 0 0 1 1 0 0 1 1 VSEL30 bit 0 1 0 1 0 1 0 1 Input Selector Off (Note: 25) VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A
(default)
Table 6. Video Input Selector 3 (VOUT3)
Note: 25. The video outputs become Hi-Z when the input selectors are off.
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[AK4220]
Input Detection Circuit, INT pin Output
The AK4220 has channel-independent audio input detection circuit and video synchronization signal detection circuit. Each input source is set as shown in Table 7 and Table 8. ADSEL2 bit 0 0 0 0 1 1 1 1 ADSEL1 bit 0 0 1 1 0 0 1 1 ADSEL0 bit 0 1 0 1 0 1 0 1 Detection Source Off LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 LIN7 / RIN7
(default)
Table 7. Audio Input Detection Selector
VDSEL2 bit 0 0 0 0 1 1 1 1
VDSEL1 bit 0 0 1 1 0 0 1 1
VDSEL0 bit 0 1 0 1 0 1 0 1
Detection Source Off VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A
(default)
Table 8. Video Synchronization Signal Detection Selector
1. ADETL bit (Lch Audio Input Detection), ADETR bit (Rch Audio Input Detection)
The audio input detection circuit samples the input signal by accuracy of 100kHz30%. If the signal over the detection reception value is detected consecutively more than the frequency set by ACT1-0 bits, ADETL-R bits become "1" and if the signal over the detection reception value isn't detected consecutively more than the frequency set by ACT1-0 bits during the time set by RTM1-0 bit, ADETL-R bits become "0". The audio input detection for L/R channels is done independently. The input reception can be adjusted in the range of 6dB from -31dBV(= +40mV0p)(typ) by LV2-0 bits. When writing to 05H(ADSEL2-0, ACT1-0, RTMI1-0 bits), the counters for the consecutive detection frequency and recovery time are reset, and ADETL/R bits are reset to "0". The setting of MADEL/R bit doesn't affect the operation of ADETL/R bit.
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[AK4220]
LV2 bit 0 0 0 0 1 1 1 1
Input Reception -6dB -3dB 0dB (default) +3dB +6dB N/A N/A N/A 0dB = +40mV0p(typ) Table 9. Level Setting of Audio Input Detection
LV1 bit 0 0 1 1 0 0 1 1
LV0 bit 0 1 0 1 0 1 0 1
ACT1 bit 0 0 1 1
ACT0 bit 0 1 0 1
Consecutive Detect Frequency 1 2 4 8
(default)
Table 10. Consecutive Detection frequency Setting of Audio Input Detection
RTM1 bit 0 0 1 1
RTM0 bit 0 1 0 1
Recovery Time (typ) 40ms 80ms 160ms 320ms
(default)
Table 11. Recovery Time Setting of Audio Input Detection
Detect Level -31dBV(default)
Input pin (ex. LIN+1)
Input signal level exceeds the detection reception value during sampling x consecutive detect frequency.
Input signal level doesn't exceeds the detection reception value during sampling x consecutive detect frequency. Recovery Time
ADETL bit
"0"
"1"
"0"
INT pin
Hi-Z (pulled-up)
"L"
Hi-Z (pulled-up)
Figure 14. Audio Detection Operation
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[AK4220]
2. VDET bit (Video Sync Signal Detection)
The video sync signal detection circuit can change the detection mode by VDMD bit. VDMD bit ="0" (default) When video sync signal above 0.07Vpp(typ) is detected, VDET bit become "1" and VDET bit returns to "0" after reading the register of 08H. The VDET bit is also reset to "0" by writing to the register of 04H with VDSEL2-0 bits. When writing to 04H(VDSEL2-0 bits) the VDET bit become "0". VDMD bit ="1" The detection circuit counts the number of video sync signal above 0.07Vpp(typ) every 40ms(30%) period generated by the internal counter. When the period with the sync of 384 or more continues tow times, the VDET bit becomes "1" after 1/2 period. When the period with the sync signal less than 384 continues tow times, the VDET bit becomes "0" after 1/2 period. The internal timer isn't reset when changing the input source. Therefore the detection time, from after changing the input source to VDET bit = "1", depends on the timing of input source change. In case of a period that the internal timer count is the shortest(40ms x 70% = 28ms), when the detection circuit counts 384 times during the first period that receives video sync signal and counts 384 times or more in the following period, the detection time becomes the shortest. Detection time (min) = (1/fH) x 384 + 28ms x 1.5 66.6ms @ fH=15.625kHz fH: frequency of video synchronization signal If a period that internal timer counts is the longest (40ms x 130% = 52ms), when the detection circuit counts only 383 times during the first period that receives video sync signal and counts 384 times or more in the following two periods, the detection time becomes the longest. Detection time (max) = (1/fH) x 384 + 52ms x 2.5 154.5ms @ fH=15.625kHz fH: frequency of video synchronization signal When writing to 04H(VDSEL2-0bits), the internal timer is reset and VDET bit becomes "0". The setting of MVDET bit doesn't affect the operation of VDET bit.
1st period
2nd period
3rd period
4th period
Input pin (ex. VIN1)
384 times 384 times
VDET bit Input pin (ex. VIN1)
384 times
"0"
"1"
384 times
384 times
VDET bit
"0"
"1"
Figure 15. VDET bit timing (VDMD bit ="1")
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[AK4220]
3. INT pin output
The output source of INT pin is ORed between ADETL/R bits and VDET bit If the output source of INT pin is "H", INT pin="L", and if the output source of INT pin is "L", INT pin="Hi-Z". If each mask bit is "1", each detection bit is masked independently and the detection result isn't reflected to INT pin.
+3.3V DVDD 10k AK4220 VDET MVDET ADETL MADETL ADETR MADETR
INT pin
DVSS
Figure 16. INT Pin Output
MVDET bit 0 0 0 0 1 1 1 1
MADETL bit 0 0 1 1 0 0 1 1
MADETR bit 0 1 0 1 0 1 0 1
INT pin output source "OR" (VDET bit, ADETL bit, ADETR bit) "OR" (VDET bit , ADETL bit) "OR" (VDET bit, ADETR bit) VDET bit "OR" (ADETL bit, ADETR bit) ADETL bit ADETR bit "L"(INT pin = "Hi-Z")
(default)
Table 12. INT Pin Output Setting
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[AK4220]
Parallel Output Circuit, INT Output Circuit, SDA Output Circuit
Q0-4 bits setting are output from Q0-4 pins. Each output is open drain. Normally connected to DVSS with a 10kohm resistance. INT pin is the same output circuit (Refer Figure 16). SDA pin is open drain output, and connected to DVSS with a resistance. Refer to I2C bus standard as for resistance value. As there is a protection between each pin and DVDD, the pulled-up voltage should be DVDD or lower. And if the pulled-up voltage is supplied from the different power supply from DVDD, only DVDD should not be powered off independently. When PDN pin ="L" and DVDD is supplied to the AK4220, the AK4220 can be in power-down state. In Power-down state, VVDD1-2 and AVDD can be powered off.
+3.3V DVDD 10k AK4220
Q0-4 pin
Q0~Q4 bit
DVSS
Figure 17. Q0-Q4 Pin Output
+3.3V DVDD AK4220
SDA pin
DVSS
Figure 18. SDA Pin Output
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[AK4220]
Serial Control Interface
1. 4 wire serial control mode (IICN pin = "H")
With the 4-wire P interface pins (CSN, CCLK, CDTI and CDTO), the data on this interface consists of the Chip address (2-bits, Fixed to "00"), Read/Write (1-bit), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The data are clocked in on the rising edge of CCLK, and data are clocked out on the falling edge of CCLK. For write operations, the data is latched after a low-to-high transition of the 16th CCLK. For read operation, the data is outputted to Hi-Z on the rising edge of CSN. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized at PDN pin = "L".
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI CDTO CDTI CDTO
WRITE
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
READ
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1,C0: R/W: A4-A0: D7-D0:
Chip Address: ( Fixed to "00") READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 19. 4-wrie Serial Control I/F Timing
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[AK4220]
2. I2C bus control mode (IICN pin = "L")
The AK4220 supports the fast-mode I2C-bus system (max: 400kHz). 1. WRITE Operations Figure 20 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 26). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as "001000". The next one bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) set these device address bits (Figure 21). If the slave address matches that of the AK4220, the AK4220 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 27). A R/W bit value of "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4220. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 22). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 23). The AK4220 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 26). The AK4220 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4220 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 08H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 28) except for the START and STOP conditions.
S T A R T S T O P Sub Address(n) A C K A C K Data(n) A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W="0"
SDA
Slave S Address
Figure 20. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
Figure 21. The First Byte
0
0
0
0
A3
A2
A1
A0
Figure 22. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Byte Structure after the second byte
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[AK4220]
2. READ Operations Set the R/W bit = "1" for the READ operation of the AK4220. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 09H prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4220 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. 2-1. CURRENT ADDRESS READ The AK4220 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4220 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4220 ceases transmission.
S T A R T
R/W="1"
S T O P Data(n+1) Data(n+2) A C K A C K Data(n+3) A C K A C K Data(n+1+x) A C K P
SDA
Slave S Address A C K
Figure 24. CURRENT ADDRESS READ
2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to "1". The AK4220 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4220 ceases transmission.
S T A R T S T A R T Sub Address(n) A C K A C K S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W="0"
R/W="1"
SDA
Slave S Address
Slave S Address
Figure 25. RANDOM ADDRESS READ
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[AK4220]
SDA
SCL S start condition P stop condition
Figure 26. START and STOP Conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION clock pulse for acknowledgement
1
2
8
9
Figure 27. Acknowledge on the I2C-Bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 28. Bit Transfer on the I2C-Bus
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[AK4220]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H Register Name Power Down & Reset Input Selector 1 Input Selector 2 Input Selector 3 Detection Control1 Detection Control2 Detection Control3 Parallel Output AV Detection D7 0 0 0 0 0 RTM1 VDMD 0 0 D6 0 VSEL12 VSEL22 VSEL32 VDSEL2 RTM0 MVDET 0 VDET D5 0 VSEL11 VSEL21 VSEL31 VDSEL1 ACT1
MADETR
D4 SAGN VSEL10 VSEL20 VSEL30 VDSEL0 ACT0
MADETL
0 ADETR
Q4 ADETL
D3 0 0 0 0 0 0 0 Q3 0
D2 0 ASEL12 ASEL22 ASEL32 0 ADSEL2 LV2 Q2 0
D1 BIAS ASEL11 ASEL21 ASEL31 0 ADSEL1 LV1 Q1 0
D0 PW ASEL10 ASEL20 ASEL30 0 ADSEL0 LV0 Q0 0
Note: When the PDN pin goes "L", the registers are initialized to their default values. The bits indicated to "0" in the register map must contain a "0" value. Do not write any data to the register over 09H.
Register Definitions
Reset & Initialize Addr 00H Register Name Power Down & Reset R/W Default D7
0
D6
0
D5
0
D4
SAGN
D3
0
D2
0
D1
BIAS
D0
PW
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 1
PW: Power bit 0: Power-down except register control block. The register don't change. (default) 1: Normal operation When PDN pin="L", PW bit becomes "1" and the registers are initialized to their default values. BIAS: Audio Bias Power bit 0: Power-down the Audio Bias Circuit (default) 1: Normal operation SAGN: Video output selector bit 0: Sag Compensation mode (default) 1: DC output mode
Addr 01H
Register Name Input Selector 1 R/W Default
D7
0
D6
VSEL12
D5
VSEL11
D4
VSEL10
D3
0
D2
ASEL12
D1
ASEL11
D0
ASEL10
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
ASEL12-10: Audio Input Selector 1 Refer Table 1 VSEL12-10: Video Input Selector 1 Refer Table 4
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[AK4220]
Addr
02H
Register Name Input Selector 2 R/W Default
D7
0
D6
VSEL22
D5
VSEL21
D4
VSEL20
D3
0
D2
ASEL22
D1
ASEL21
D0
ASEL20
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
ASEL22-20: Audio Input Selector 2 Refer Table 2 VSEL22-20: Video Input Selector 2 Refer Table 5
Addr
03H
Register Name Input Selector 3 R/W Default
D7
0
D6
VSEL32
D5
VSEL31
D4
VSEL30
D3
0
D2
ASEL32
D1
ASEL31
D0
ASEL30
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
ASEL32-30: Audio Input Selector 3 Refer Table 3 VSEL32-30: Video Input Selector 3 Refer Table 6
Addr
04H
Register Name Detection Control1 R/W Default
D7
0
D6 R/W 0
D5 R/W 0
D4 R/W 0
D3
0
D2
0
D1
0
D0
0
VDSEL2 VDSEL1 VDSEL0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
VDSEL2-0: Video Synchronization Signal Detection Selector Refer Table 8
Addr 05H
Register Name Detection Control2 R/W Default
D7
RTM1
D6
RTM0
D5
ACT1
D4
ACT0
D3
0
D2 R/W 0
D1 R/W 0
D0 R/W 0
ADSEL2 ADSEL1 ADSEL0
R/W 0
R/W 1
R/W 0
R/W 0
R/W 0
ADSEL2-0: Audio Input Detection Selector Refer Table 7 ACT1-0: Audio Input Continuous Detection times Setting Refer Table 10 RTM1-0: Audio Input Detection Recovery time Setting Refer Table 11
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[AK4220]
Addr
06H
Register Name Detection Control3 R/W Default
D7
VDMD
D6 R/W 0
D5 R/W 0
D4 R/W 0
D3
0
D2
LV2
D1
LV1
D0
LV0
MVDET MADETR MADETL
R/W 0
R/W 0
R/W 0
R/W 1
R/W 0
LV2-0: Audio Input Detection Level Setting Refer Table 9 MADETL/R: Audio Input Detection Mask Setting for Lch/Rch Refer Table 12 MVDET: Video Synchronization Signal Detection Mask Setting Refer Table 12 VDMD: Video Synchronization Signal Detection Mode Setting "0": If video signal above 0.07Vpp(typ) is detected VDET bit becomes "1" and when reading 08H VDET bit becomes "0". (default) "1": Refer VDET bit (Video Synchronization Signal Detection) section (Page19).
Addr
07H
Register Name Parallel Output R/W Default Q4-0: Parallel Output Setting "1": Hi-Z(default) "0": "L" Output
D7
0
D6
0
D5
0
D4
Q4
D3
Q3
D2
Q2
D1
Q1
D0
Q0
R/W 0
R/W 0
R/W 0
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
Addr
08H
Register Name AV Detection R/W Default
D7
0
D6
VDET
D5
ADETR
D4
ADETL
D3
0
D2
0
D1
0
D0
0
READ 0
READ 0
READ 0
READ 0
READ 0
READ 0
READ 0
READ 0
ADETL/R: Audio Input Detection States for Lch/Rch "0": Undetected (default) "1": Detected VDET: Video Synchronization Signal Detection States "0": Undetected (default) "1": Detected Writing to address 08H will be ignored.
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[AK4220]
SYSTEM DESIGN
Figure 29 shows the system connection diagram. An evaluation board [AKD4220] is available which demonstrates the optimum layout, power supply arrangements and measurement results.
Digital Ground
Analog Ground
0.47u
Audio in
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u
0.47u RIN+2 50
GND7 63
RIN+6 62
LIN+6 61
GND6 60
RIN+5 59
LIN+5 58
GND5 57
RIN+4 56
LIN+4 55
GND4 54
RIN+3 53
LIN+3 52
GND3 51
LIN+2 49
LIN+7 64
0.47u
1 RIN+7 2 PDN
GND2 48 RIN+1 47 LIN+1 46 GND1 45 ROUT3 44 LOUT3 43 ROUT2 42
0.47u 0.47u 0.47u 0.47u 10u 10u 10u 10u 10u 10u 300 300 300 300 300 300
Audio in
Micro Controller
3 CAD1 4 SCL 5 SDA 6 CAD0 7 INT
External Block
8 Q0 9 Q1 10 Q2 11 Q3
AK4220
LOUT2 41 ROUT1 40 LOUT1 39 AVSS 38 VCOM 37 MUTET 36 R 35
Audio out
Digital 3.3V
10k
10u +
0.1u
12 Q4 13 DVDD 14 DVSS 15 VOUT1 21 VOUT3 18 VOUT2 20 VVDD2 27 VVDD1 23 VVSS2 25 VVSS3 29 VVSS1 16 VFB1 17 TEST 19 VFB2 22 VFB3
+ 0.1u 2.2u 12k 1u
+ AVDD 34 0.1u 10u VIN6 33 30 VIN4 32 VIN5 31 IICN
Analog 5V
24 VIN1
26 VIN2 0.1u
10u 0.1u
+
10u 0.1u 0.1u
+
0.1u
28 VIN3
75 0.1u
75 0.1u
100u
100u
100u
2.2u
2.2u
2.2u
75
75
75
Video out Analog 5V
75
75
Video in
Figure 29. Typical Connection Diagram
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[AK4220]
1. Grounding and Power Supply Decoupling
The AK4220 requires careful attention to power supply and grounding arrangements. AVDD, VVDD1-2 and DVDD are usually supplied from the analog power supply in the system. Alternatively if AVDD, VVDD1-2 and DVDD are supplied separately, the power up sequence is not critical. AVSS, VVSS1-3 and DVSS must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4220 as possible, with the small value ceramic capacitors being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached between VCOM and AVSS eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from VCOM in order to avoid unwanted coupling into the AK4220. MUTET is an audio output common voltage. A 0.1F electrolytic capacitor attached between VCOM and AVSS. No load current may be drawn from MUTET. All signals, especially clocks, should be kept away from MUTET in order to avoid unwanted coupling into the AK4220.
3. The notes for drawing the board
Analog input and output pins should be as short as possible in order to avoid unwanted coupling into the AK4220. The unused pins should be open.
4. Video Output
The AK4220 has on-chip 3ch video amp for drive 150 resistance and two way to output video signal. One way is using the Sag Compensation circuit (Figure 30), the other way is using DC output (Figure 31). 100F and 2.2F capacitors is needed for Sag Compensation circuit . It should be shorted VOUT pin and VBF pin using DC output mode. The clamp level is 600mV(typ) in the DC output mode. Each output way can set by SAGN bit (Table 13).
C3 100uF +6dB VOUT VFB C4 2.2uF R1 75 R2 75
Figure 30. Video Block (SAGN bit="0", Sag Compensation mode)
R1 75 +6dB VOUT VFB R2 75
Figure 31. Video Block (SAGN bit="1", DC Output)
SAGN bit 0 1
Output Sag Compensation mode DC output mode
(default)
Table 13. Setting for the video output
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[AK4220]
PACKAGE
64pin LQFP(Unit:mm)
12.0 0.3 10.0 48 49 33 32
1.70MAX 0.10 0.05
1.40 -0.05
+0.05
64 1 0.5 0.22 0.05 16
17
12.0 0.3
10.0
0.17 0.05 0.10 M
0 10
0.10
0.5 0.2
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
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[AK4220]
MARKING
AK4220VQ XXXXXXX
1
1) Pin #1 indication 2) Asahi Kasei Logo 3) Marking Code: AK4220VQ 4) Date Code: XXXXXXX (7 digits)
AKM
REVISION HISTORY
Date (YY/MM/DD) 07/05/10 Revision 00 Reason First Edition Page Contents
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[AK4220]
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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